--library STD; -- you don't need STD, it is automatic library IEEE; -- but may need other libraries use IEEE.std_logic_1164.all; -- basic logic types USE work.STD_ARITH.all; entity IO is port( Clk1: in std_logic; -- Osc clock 1 (20MHz) Clk2: in std_logic; -- Osc clock 2 (20MHz / 2n) ISAClk: in std_logic; led1: out std_logic; -- Led 1 led2: out std_logic; -- Led 1 led3: out std_logic; -- Led 1 Con1: out std_logic_vector(7 downto 0); -- Connector1 Con2: in std_logic_vector(7 downto 0); -- Connector2 Con3: out std_logic_vector(7 downto 0); -- Connector3 Con4: in std_logic_vector(7 downto 0); -- Connector4 Ad: in std_logic_vector(9 downto 0); -- ISA Adress Data: inout std_logic_vector(7 downto 0); AEN: in std_logic; -- Adress Enable IOR,IOW: in std_logic; -- Synchronisation signals RESET_PCF : out std_logic; CS_PCF : buffer std_logic; PCFClk : buffer std_logic); attribute pin_numbers of IO: entity is "Clk1:62 Clk2:65 ISAClk:23" &" led1:10 led2:12 led3:13" &" Ad(9):31 Ad(8):33 Ad(7):34 Ad(6):36 Ad(5):37 Ad(4):38 Ad(3):39 Ad(2):40 Ad(1):45 Ad(0):46" &" IOW:20 IOR:15" &" Data(7):19 Data(6):24 Data(5):25 Data(4):26 Data(3):27 Data(2):28 Data(1):29 Data(0):30" &" Con1(7):47 Con1(6):56 Con1(5):48 Con1(4):55 Con1(3):49 Con1(2):54 Con1(1):50 Con1(0):52" &" Con2(7):57 Con2(6):68 Con2(5):58 Con2(4):67 Con2(3):59 Con2(2):66 Con2(1):60 Con2(0):61" &" Con3(7):69 Con3(6):78 Con3(5):70 Con3(4):77 Con3(3):71 Con3(2):76 Con3(1):73 Con3(0):75" &" Con4(7):79 Con4(6):6 Con4(5):80 Con4(4):5 Con4(3):81 Con4(2):4 Con4(1):82 Con4(0):3" &" AEN:16" &" RESET_PCF:7 CS_PCF:9 PCFClk:8"; end IO; architecture arch_IO of IO is -- where declarations are placed -- Internal signals signal AdressPC : std_logic_vector(1 downto 0); -- Current adress for the PC signal AdressMC1 : std_logic_vector(1 downto 0); -- Current adress for the PC signal AdressMC2 : std_logic_vector(1 downto 0); -- Current adress for the PC signal NumReg : std_logic_vector(2 downto 0); -- Current register signal CS30E : std_logic; -- Chip select Adress 0x30E signal CS30F : std_logic; -- Chip select Adress 0x30F signal CS310 : std_logic; -- Chip select Adress 0x310 signal CS311 : std_logic; -- Chip select Adress 0x311 signal CS312,CS : std_logic; -- Chip select Adress 0x312 signal Reg0 : std_logic_vector(7 downto 0); -- Registers 0 signal Reg1 : std_logic_vector(7 downto 0); -- Registers 1 signal Reg2 : std_logic_vector(7 downto 0); -- Registers 2 signal Reg3 : std_logic_vector(7 downto 0); -- Registers 3 signal Encoder0 : std_logic_vector(7 downto 0); signal Encoder1 : std_logic_vector(7 downto 0); signal Encoder2 : std_logic_vector(7 downto 0); signal Encoder3 : std_logic_vector(7 downto 0); signal Tampon : std_logic_vector(7 downto 0); signal Status : std_logic_vector(7 downto 0); -- Status Registers attribute synthesis_off of CS30E: signal is true; -- Adress 0x300 attribute synthesis_off of CS30F: signal is true; -- Adress 0x301 attribute synthesis_off of CS310: signal is true; -- Adress 0x301 attribute synthesis_off of CS311: signal is true; -- Adress 0x301 attribute synthesis_off of CS312: signal is true; -- Adress 0x301 attribute synthesis_off of status: signal is true; attribute synthesis_off of tampon: signal is true; --attribute lab_force of tampon: signal is "G"; begin ------------------------------ Status of the leds ------------------------------------ led1<= NOT (CS30E and CS30F and CS310 and CS311 and CS312 and CS_PCF); led2<=Status(0); led3<=Status(1); ------------------------- COMMUNICATION WITH THE PC ---------------------------------- -- Chip selection CS30E<='0' when (Ad="1100001110") AND (AEN='0') else '1'; CS30F<='0' when (Ad="1100001111") AND (AEN='0') else '1'; CS310<='0' when (Ad="1100010000") AND (AEN='0') else '1'; CS311<='0' when (Ad="1100010001") AND (AEN='0') else '1'; CS312<='0' when (Ad="1100010010") AND (AEN='0') else '1'; -- The PC is writing in the registers process (IOW) begin if (IOW'event and IOW='1') then -- Register writing if (CS30E='0') then Reg0<=Data; end if;--else if (CS30F='0') then Reg1<=Data; end if; if (CS310='0') then Reg2<=Data; end if; if (CS311='0') then Reg3<=Data; end if; if (CS312='0') then Status(0)<=Data(0); Status(1)<=Data(1); Status(2)<=Data(2); end if; end if; end process; --circuit bidirectionnel Data<= Encoder0 when ((CS30E='0') and (IOR='0')) else Encoder1 when ((CS30F='0') and (IOR='0')) else tampon when (CS='0') else "ZZZZZZZZ"; CS<='0' when ((CS312='0') and(CS310='0') and (IOR='0')) else '1'; Tampon<= Status when (CS312='0') else Encoder2 when (CS310='0') else Encoder3; ------------------------- COMMUNICATION WITH THE µC ---------------------------------- Con1<=Reg0 when Con2(0)='0' else Reg1; Con3<=Reg2 when Con4(0)='0' else Reg3; Status(3)<=Con2(1); Status(4)<=Con2(2); Status(5)<=Con4(1); Status(6)<=Con4(2); Status(7)<='0'; ------------------------- COMMUNICATION WITH THE I2C ---------------------------------- process(ISAClk) -- Divide by 2 the ISA frequency for the PCF begin if(ISAClk'event and ISAClk='1') then PCFClk <= Not(PCFClk); end if; end process; RESET_PCF<=Status(2); -- Set the reset of the PCF8584 CS_PCF<='0' when (Ad="1100001100" or Ad="1100001101") and (AEN='0') else '1'; -- Enable the Chip Select if necessary ------------------------- Encoders ---------------------------------- process(Con2(3)) -- Counter 1 begin if(Con2(3)'event and Con2(3)='1') then if (Con2(5)='1') then Encoder0<=Encoder0+1; else Encoder0<=Encoder0-1; end if; end if; end process; process(Con2(4)) -- Counter 2 begin if(Con2(4)'event and Con2(4)='1') then if (Con2(6)='1') then Encoder1<=Encoder1+1; else Encoder1<=Encoder1-1; end if; end if; end process; process(Con4(3)) -- Counter 1 begin if(Con4(3)'event and Con4(3)='1') then if (Con4(5)='1') then Encoder2<=Encoder2+1; else Encoder2<=Encoder2-1; end if; end if; end process; process(Con4(4)) -- Counter 2 begin if(Con4(4)'event and Con4(4)='1') then if (Con4(6)='1') then Encoder3<=Encoder3+1; else Encoder3<=Encoder3-1; end if; end if; end process; end architecture arch_IO;